The present invention relates generally to a design of a semiconductor circuit, and more particularly to a technology of designing the semiconductor circuit, especially designing a circuit layout.
As micronization of LSI has advanced over the recent years, circuit characteristics have been greatly affected by accuracy of physical quantities of a shape of layout pattern, arranging positions, etc of circuit devices(circuit elements) or by variations in these physical quantities in a manufacturing process. Further, such a method was also proposed that the circuit characteristics are optimized by taking the affection thereof into prediction of the circuit characteristics.
A conventional technology is not, however, sufficient in terms of optimizing the circuit characteristics of a design target circuit as a whole including a multiplicity of devices and wirings due to a heavy load of calculation quantity. For example, the circuit design arranges a layout of a gate, a gate dimension, a gate width, etc in a way that takes a balance between a current driving force of each transistor and the load into consideration. A technology of determining the optimum gate dimension and gate width in the design target circuit as a whole, is not yet actualized.
Further, in the recent transistor, there exists a case in which the current driving force differs in the transistors having the same gate width and the same gate length, depending on a variation of device isolation patterns due to affection by a stress of a device isolation oxide film. The balance between the current driving force and the load in the actual circuit, which was taken into consideration when making the layout, might be lost. Moreover, an analysis taking a plurality of circuit characteristics simultaneously into consideration, for example, a scheme of properly determining the gate length of each of the transistors of the circuit on the basis of a trade-off relationship between power consumption and circuit delay time, is not yet provided.